library ieee;
use ieee.std_logic_1164.all;

entity maindec is
port (  op		: in std_logic_vector(5 downto 0);
		aluop		: out std_logic_vector(1 downto 0);
        memToReg, memWrite, branch, aluSrc, regDst, regWrite, jump	: out std_logic);
end entity;

architecture arch of maindec is
begin
    process (op)
    begin
        if (op = "000000") then
       		aluop <= "10";
       		memToReg <= '0';
       		memWrite <= '0';
       		branch <= '0';
       		aluSrc <= '0';
       		regDst <= '1';
       		regWrite <= '1';
       		jump <= '0';
        elsif (op = "100011") then
        	aluop <= "00";
       		memToReg <= '1';
       		memWrite <= '0';
       		branch <= '0';
       		aluSrc <= '1';
       		regDst <= '0';
       		regWrite <= '1';
       		jump <= '0';
        elsif (op = "101011") then
	    	aluop <= "00";
       		memToReg <= '0';
       		memWrite <= '1';
       		branch <= '0';
       		aluSrc <= '1';
       		regDst <= '0';
       		regWrite <= '0';
       		jump <= '0';
	    elsif (op = "000100") then
	   		aluop <= "01";
       		memToReg <= '0';
       		memWrite <= '0';
       		branch <= '1';
       		aluSrc <= '0';
       		regDst <= '0';
       		regWrite <= '0';
       		jump <= '0';
	    elsif (op = "001000") then
	   		aluop <= "00";
       		memToReg <= '0';
       		memWrite <= '0';
       		branch <= '0';
       		aluSrc <= '1';
       		regDst <= '0';
       		regWrite <= '1';
       		jump <= '0';
	    elsif (op = "000010") then
	    	aluop <= "00";
       		memToReg <= '0';
       		memWrite <= '0';
       		branch <= '0';
       		aluSrc <= '0';
       		regDst <= '0';
       		regWrite <= '0';
       		jump <= '1';
	   	end if;
    end process;
end architecture;
